An Area/Delay Efficient Dual-Modular Flip-Flop with Higher SEU/SET Immunity

According to the process scaling, semiconductor devices are becoming more sensitive to soft errors since amount of critical charges are decreasing. In this paper, we propose an area/delay efficient dual modular flip-flop, which is tolerant to SEU (Single Event Upset) and SET (Single Event Transient). It is based on a "BISER" (Built-in Soft Error Resilience). The original BISER FF achieves small area but it is vulnerable to an SET pulse on C-elements. The proposed dual modular FF doubles C-elements and weak keepers between master and slave latches, which enhances SET immunity considerably with paying small area-delay product than the conventional delayed TMR FFs.