High Speed, High Resolution and Low Power Approaches for SAR A/D Converter

Through the review and analysis of traditional and some recently reported conversion methods in SAR A/D converters, high speed, high resolution and low power approaches for SAR A/D converter are discussed. Based on SMIC 65nm CMOS technology, two typical low power methods reported in previous works are validated by circuit design and simulation. Design challenges and considerations of high speed SAR A/D converter are presented. Moreover, C-R combination based high resolution approach is discussed. Finally, a novel R-C combination based method is also addressed and a 10-bit SAR A/D converter with this approach is implemented in SMIC 90nm CMOS process.

[1]  Yuriy Greshishchev,et al.  A 24GS/s 6b ADC in 90nm CMOS , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[2]  Bruce E. Peetz Dynamic Testing of Waveform Recorders , 1983, IEEE Transactions on Instrumentation and Measurement.

[3]  B.P. Ginsburg,et al.  Dual Time-Interleaved Successive Approximation Register ADCs for an Ultra-Wideband Receiver , 2007, IEEE Journal of Solid-State Circuits.

[4]  Yan Xiao,et al.  A Novel R-C Combination Based Pseudo-differential SAR A/D Converter in 90nm CMOS Process , 2009, 2009 Pacific-Asia Conference on Circuits, Communications and Systems.

[5]  A. Matsuzawa Trends in high speed ADC design , 2007, 2007 7th International Conference on ASIC.

[6]  Jens Sauerbrey,et al.  A 0.5-V 1-μW successive approximation ADC , 2003, IEEE J. Solid State Circuits.

[7]  Yintang Yang,et al.  Low-power Capacitor Arrays for Charge Redistribution SAR A-D Converter in 65nm CMOS , 2009, 2009 Pacific-Asia Conference on Circuits, Communications and Systems.

[8]  Reimund Wittmann,et al.  Statistical averaging based linearity optimization for resistor string DAC architectures in nanoscale processes , 2008, 2008 IEEE International SOC Conference.

[9]  W. Black,et al.  Time interleaved converter arrays , 1980, 1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[10]  Haigang Yang,et al.  Design of an embedded CMOS CR SAR ADC for low power applications in bio-sensor SOC , 2007, 2007 7th International Conference on ASIC.

[11]  ハリ、ラパッコ Touch-Screen Controller , 2009 .

[12]  B.P. Ginsburg,et al.  A 500MS/s 5b ADC in 65nm CMOS , 2006, 2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers..

[13]  Ran Feng,et al.  IC Design of 2Ms/s 10-bit SAR ADC with Low Power , 2007, 2007 International Symposium on High Density packaging and Microsystem Integration.

[14]  Gabor C. Temes,et al.  An 8-b 1.3-MHz successive-approximation A/D converter , 1990 .

[15]  B.P. Ginsburg,et al.  Highly Interleaved 5-bit, 250-MSample/s, 1.2-mW ADC With Redundant Channels in 65-nm CMOS , 2008, IEEE Journal of Solid-State Circuits.

[16]  Doris Schmitt-Landsiedel,et al.  A 0.5V, 1µW successive approximation ADC , 2002 .