Scaling of process technology is inevitably accompanied by the increase of local variation in transistor characteristics, which has been deteriorating the operation margin of SRAM. This trend necessitates assist circuits for SRAM to increase the immunity against variations, and many papers in this area [1-4] have been published. In this paper, we present an assist circuit suitable for the SRAMs in 20nm generation. Figure 13.3.1 compares local variations of SRAM cell transistors, pass-gate NMOS (PG), pull-down NMOS (PD) and pull-up PMOS (PU) for 28 and 20nm, showing degradation as the process advances. Noticeably, the NMOS transistors become worse than PMOS, which causes degradation in SRAM operating margin since SRAM characteristics such as static noise margin (SNM) are more sensitive to NMOS than PMOS. Figure 13.3.1 also shows the operational window enclosed by read and write immunity against local variations in 28 and 20nm. This indicates assist circuits must perform beyond the level established in previously published work to address SRAM variation in advanced technology nodes. Lowering wordline (WL) voltage level is one of the read-assist approaches. Lowering the supply voltage of PU in a cell (ARVDD) and negative bitline (BL) techniques are known to be effective for the write operation. These techniques, however, have side-effects: lowering the WL voltage degrades write margin and lowering ARVDD leads to higher power consumption and a long cycle-time. Furthermore, the negative BL technique can cause write errors in non-selected columns. Thus, it is necessary to select which assist technique should be applied depending on each process technology. In addition, the SRAM used in production generally include single-port SRAM (SP-SRAM) and dual-port SRAM (DP-SRAM), so the assist circuits to be applied should be effective for whole SRAM family.
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