All digital phase-locked loop: concepts, design and applications

The concepts of an all digital phase-locked loop (DPLL), which contains a purely digital phase detector, loop filter and voltage-controlled oscillator, are explained. A second order DPLL is considered and analysed using the Z-transform technique. Implementation of the DPLL, based on the CMOS digital signal processor TMS 320C25, and the experimental results, are presented. Potential applications are also discussed.

[1]  J. Garodnick,et al.  Response of an All Digital Phase-Locked Loop , 1974, IEEE Trans. Commun..

[2]  Floyd M. Gardner,et al.  Phaselock techniques , 1984, IEEE Transactions on Systems, Man, and Cybernetics.

[3]  W. Mecklenbrauker,et al.  Remarks on the zero-input behavior of second-order digital filters designed with one magnitude trunc , 1975 .

[4]  W.C. Lindsey,et al.  A survey of digital phase-locked loops , 1981, Proceedings of the IEEE.

[5]  C. K. Yuen,et al.  Theory and Application of Digital Signal Processing , 1978, IEEE Transactions on Systems, Man, and Cybernetics.