Left to right serial multiplier for large numbers on FPGA

A new high precision serial multiplier with most significant digit first (MSDF) is presented. This one uses a borrow-save (BS) adder to perform the reduction of large length partials products required by the multiplication of large numbers. The results are converted from BS form to the 2's complement representation by the on-the-fly conversion which let the conversion of the digit result as soon as it is obtained. It is shown that the comparison between the residual and these constants (-3/2, -1/2, 1/2 and 3/2) needed in the radix-2 on line multiplication, present problem in high precision computation. However, in the proposed method the operands are introduced digit by digit with MSDF mode and results are obtained in the same manner with fixed time delay independently of the operand size. So, this approach is advantageously used for the long multiplication computation. This method has been tested by the execution of a program developed with Maple 9.5 for several test vectors. A generic VHDL code is described for the multiplier architecture. The results of the implementation of this multiplier for several operands sizes (128, 256, 512, and 1024) on Virtex-II FPGA Circuit confirm that the multiplication is performed in constant time.

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