A Landscape of the New Dark Silicon Design Regime

Because of the breakdown of Dennard scaling, the percentage of a silicon chip that can switch at full frequency drops exponentially with each process generation. This utilization wall forces designers to ensure that, at any point in time, large fractions of their chips are effectively "dark silicon"--that is, significantly underclocked or idle for large periods of time. As exponentially larger fractions of a chip's transistors become dark, silicon area becomes an exponentially cheaper resource relative to power and energy consumption. This shift is driving a new class of architectural techniques that "spend" area to "buy" energy efficiency. All these techniques seek to introduce new forms of heterogeneity into the computational stack. This article begins by examining four promising directions--the "four horsemen"--that have emerged as top contenders for thriving in the dark silicon age. Each direction carries with its virtues deep-seated restrictions that require a careful understanding of the underlying trade-offs and benefits. Furthermore, the author proposes a set of evolutionary dark silicon design principles and examines how one of the "darkest" computing architectures of all, the human brain, trades off energy and area in ways that provide potential insights into more revolutionary directions for computer architecture.

[1]  Adrian M. Ionescu,et al.  Tunnel field-effect transistors as energy-efficient electronic switches , 2011, Nature.

[2]  Michael Bedford Taylor,et al.  Is dark silicon useful? Harnessing the four horsemen of the coming dark silicon apocalypse , 2012, DAC Design Automation Conference 2012.

[3]  Luis Ceze,et al.  Neural Acceleration for General-Purpose Approximate Programs , 2014, IEEE Micro.

[4]  Karthikeyan Sankaralingam,et al.  Dark Silicon and the End of Multicore Scaling , 2012, IEEE Micro.

[5]  Amin Ansari,et al.  Bundled execution of recurring traces for energy-efficient general purpose processing , 2011, 2011 44th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[6]  Babak Falsafi,et al.  Toward Dark Silicon in Servers , 2011, IEEE Micro.

[7]  Vikram Bhatt,et al.  The GreenDroid Mobile Application Processor: An Architecture for Silicon's Dark Future , 2011, IEEE Micro.

[8]  Kevin Skadron,et al.  Scaling with Design Constraints: Predicting the Future of Big Chips , 2011, IEEE Micro.

[9]  R.H. Dennard,et al.  Design Of Ion-implanted MOSFET's with Very Small Physical Dimensions , 1974, Proceedings of the IEEE.

[10]  Vladimir Stojanovic,et al.  Demonstration of integrated micro-electro-mechanical switch circuits for VLSI applications , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

[11]  David Blaauw,et al.  Near-Threshold Computing: Reclaiming Moore's Law Through Energy Efficient Integrated Circuits , 2010, Proceedings of the IEEE.

[12]  Steven Swanson,et al.  Efficient complex operators for irregular codes , 2011, 2011 IEEE 17th International Symposium on High Performance Computer Architecture.

[13]  Karthikeyan Sankaralingam,et al.  Dynamically Specialized Datapaths for energy efficient computing , 2011, 2011 IEEE 17th International Symposium on High Performance Computer Architecture.

[14]  David Blaauw,et al.  Centip3De: A 3930DMIPS/W configurable near-threshold 3D stacked system with 64 ARM Cortex-M3 cores , 2012, 2012 IEEE International Solid-State Circuits Conference.

[15]  Steven Swanson,et al.  GreenDroid: A mobile application processor for a future of dark silicon , 2010, 2010 IEEE Hot Chips 22 Symposium (HCS).

[16]  Marios C. Papaefthymiou,et al.  Computational sprinting , 2012, IEEE International Symposium on High-Performance Comp Architecture.

[17]  Steven Swanson,et al.  Conservation cores: reducing the energy of mature computations , 2010, ASPLOS XV.

[18]  Michael Taylor A landscape of the new dark silicon design regime , 2014, DATE 2014.

[19]  Patrick Chiang,et al.  Synctium: a Near-Threshold Stream Processor for Energy-Constrained Parallel Applications , 2010, IEEE Computer Architecture Letters.