Time-Efficient Modeling and Simulation of True Workload Dependency for BTI-Induced Degradation in Processor-Level Platform Specifications

As semiconductor technology nodes approach scale to the deep submicron range, bias temperature instability (BTI)-induced degradation threatens the functional and parametric correctness of a digital design. In order to mitigate the negative consequences, a platform-level analysis should be enabled, early in the platform design trajectory. Unfortunately, today’s industrial EDA flows can only achieve this for large netlists by abstracting most of the workload-dependent impact. And, BTI is very workload-dependent in nature due to the partial recovery of the induced degradation during stress. In this chapter, we propose a global analysis flow which captures all of the relevant workload dependency, while still sustaining an acceptable execution time for platform netlists containing millions of devices.

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