Fail-Safe Realization of Sequential Machines

It is known that a sequential machine is realized by a binary sequential circuit (BSC). In this paper we try to construct a fail-safe BSC realizing a given sequential machine with the additional constraint that its output either takes the correct value or fails from 0 to 1 if the outputs of logic components in BSC, such as AND, OR, NOT gates and DELAY elements, fail asymmetrically from 0 to 1. The word “fail-safe≓ means that the failure 0 → 1 is considered safe while the reverse is not. It is rather easy to construct a fail-safe BSC for a given sequential machine. The main purpose of this paper is to construct a fail-safe BSC with the smallest number of DELAY's. First we construct a positive BSC with the smallest number of DELAY's. A BSC is positive if its logic components are all positive. Positive BSC's are fail-safe but the converse is not true. Then we also construct a fail-safe BSC with the smallest number of DELAY's. We see that the procedure for the latter construction is more complicated than the former.