Defect diagnosis based on DFM guidelines

Following design-for-manufacturability (DFM) guidelines during chip design can lower the possibility of occurrence of systematic defects. In this paper, we investigate the use of DFM guidelines during the defect diagnosis process with the goal of identifying which DFM guidelines are responsible for the defects present in failing chips. We also introduce a new metric called diagnostic coefficient that allows us to rank the guidelines according to their contribution of hard-to-diagnose defects. DFM guidelines that are ranked high should be applied during chip design in order to obtain chips that are easier to diagnose.

[1]  D. Sylvester.  Design for manufacturability: challenges and opportunities , 2005, 2005 6th International Conference on ASIC.

[2]  Artur Balasinski.  Question: DRC or DfM? Answer: FMEA and ROI , 2006, 7th International Symposium on Quality Electronic Design (ISQED'06).

[3]  Leendert M. Huisman,et al.  Diagnosing combinational logic designs using the single location at-a-time (SLAT) paradigm , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[4]  Venkatram Krishnaswamy,et al.  A study of bridging defect probabilities on a Pentium (TM) 4 CPU , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[5]  Srikanth Venkataraman,et al.  A technique for logic fault diagnosis of interconnect open defects , 2000, Proceedings 18th IEEE VLSI Test Symposium.

[6]  James E. Stine,et al.  A framework for high-level synthesis of system on chip designs , 2005, 2005 IEEE International Conference on Microelectronic Systems Education (MSE'05).

[7]  Hua Su,et al.  A statistical method for reducing systematic defects in the initial stages of production , 2002, 13th Annual IEEE/SEMI Advanced Semiconductor Manufacturing Conference. Advancing the Science and Technology of Semiconductor Manufacturing. ASMC 2002 (Cat. No.02CH37259).

[8]  Irith Pomeranz,et al.  A diagnostic test generation procedure based on test elimination byvector omission for synchronous sequential circuits , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[9]  Irith Pomeranz,et al.  Testing for systematic defects based on DFM guidelines , 2007, 2007 IEEE International Test Conference.

[10]  Janusz Rajski,et al.  Analyzing Volume Diagnosis Results with Statistical Learning for Yield Improvement , 2007, 12th IEEE European Test Symposium (ETS'07).

[11]  Irith Pomeranz,et al.  A test generation procedure for avoiding the detection of functionally redundant transition faults , 2006, 24th IEEE VLSI Test Symposium.

[12]  J.A. Waicukauski,et al.  Failure diagnosis of structured VLSI , 1989, IEEE Design & Test of Computers.

[13]  Sandeep Kumar Goel,et al.  Bridging DFM Analysis and Volume Diagnostics for Yield Learning - A Case Study , 2009, 2009 27th IEEE VLSI Test Symposium.