New parallel architecture of the DCT and its inverse for image compression

This paper proposes a novel implementation of the Discrete Cosine Transform (DCT) and its inverse (IDCT) for image compression based on the Weiping Li algorithm. The proposed architecture uses only seven parallel constant multipliers. These multipliers are implemented using the optimized DADDA multiplier structure resulting in minimal silicon occupation area. The resulted design, has a regular structure, simple control and interconnects, and efficient implementation of the inverse transform using the same hardware. The implementation is achieved in a single XC4036exHQ304 FPGA of Xilinx from VHDL description.