Circuit sensitivity to interconnect variation

Deep submicron technology makes interconnect one of the main factors determining the circuit performance. Previous work shows that interconnect parameters exhibit a significant amount of spatial variation. In this work, we develop approaches to study the influence of the interconnect variation on circuit performance and to evaluate the circuit sensitivity to interconnect parameters. First, an accurate interconnect modeling technique is presented, and an interconnect model library is developed. Then, we explore an approach using parameterized interconnect models to study circuit sensitivity via a ring oscillator circuit. Finally, we present an alternative approach using statistical experimental design techniques to study the sensitivity of a large and complicated circuit to interconnect variations.

[1]  Jacob K. White,et al.  FastCap: a multipole accelerated 3-D capacitance extraction program , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[2]  H. B. Bakoglu,et al.  Circuits, interconnections, and packaging for VLSI , 1990 .

[3]  Andrzej J. Strojwas,et al.  VLSI Yield Prediction and Estimation: A Unified Framework , 1986, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[4]  Paul Anderson,et al.  The UNIX C shell field guide , 1986 .

[5]  R.H. Dennard,et al.  Design Of Ion-implanted MOSFET's with Very Small Physical Dimensions , 1974, Proceedings of the IEEE.

[6]  Robert Spence,et al.  Tolerance Design of Electronic Circuits , 1997 .

[7]  Armen H. Zemanian,et al.  Three-dimensional capacitance computations for VLSI/ULSI interconnections , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[8]  Lynn Conway,et al.  Introduction to VLSI systems , 1978 .

[9]  J. C. Zhang,et al.  Design of experiments approach to gradient estimation and its application to CMOS circuit stochastic optimization , 1991, 1991., IEEE International Sympoisum on Circuits and Systems.

[10]  Ping Yang,et al.  An Integrated and Efficient Approach for MOS VLSI Statistical Circuit Design , 1986, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[11]  Alberto L. Sangiovanni-Vincentelli,et al.  Computing parametric yield accurately and efficiently , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[12]  A. Sangiovanni-Vincentelli,et al.  An analytical-model generator for interconnect capacitances , 1991, Proceedings of the IEEE 1991 Custom Integrated Circuits Conference.

[13]  Ken Lee,et al.  Interconnect modeling and design in high-speed VLSI/ULSI systems , 1992, Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors.

[14]  Andrzej J. Strojwas.  Selected papers on statistical design of integrated circuits , 1987 .

[15]  Armen H. Zemanian,et al.  A finite-difference procedure for the exterior problem inherent in capacitance computations for VLSI interconnections , 1988 .

[16]  Ken Lee,et al.  HIVE: an efficient interconnect capacitance extractor to support submicron multilevel interconnect designs , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[17]  Costas J. Spanos,et al.  DORIC: design of optimal and robust integrated circuits , 1994, Proceedings of IEEE Custom Integrated Circuits Conference - CICC '94.