Putting the Squeeze OB Test Sequences

Dynamic test sequence compaction is an effective means of reducing test application time and often results in higher fault coverages and reduced test generation time as well. A new algorithm for dynamic test sequence compaction is presented that uses genetic techniques to evolve test sequences. Test sequences provided by a test generator and previously evolved sequences already included in the test set are used as seeds in the genetic population. Significant improvements in test set size, fault coverage, and test generation time have been obtained over previous approaches.

[1]  M. Abramovici,et al.  SMART And FAST: Test Generation for VLSI Scan-Design Circuits , 1986, IEEE Design & Test of Computers.

[2]  Melvin A. Breuer,et al.  Digital systems testing and testable design , 1990 .

[3]  Irith Pomeranz,et al.  COMPACTEST: A METHOD TO GENERATE COMPACT TEST SETS FOR COMBINATIONAL CIRCUITS , 1991, 1991, Proceedings. International Test Conference.

[4]  Irith Pomeranz,et al.  On generating compact test sequences for synchronous sequential circuits , 1995, Proceedings of EURO-DAC. European Design Automation Conference.

[5]  Anand Raghunathan,et al.  Dynamic test sequence compaction for sequential circuits , 1996, Proceedings of 9th International Conference on VLSI Design.

[6]  W.-T. Cheng,et al.  The BACK algorithm for sequential test generation , 1988, Proceedings 1988 IEEE International Conference on Computer Design: VLSI.

[7]  Anand Raghunathan,et al.  Acceleration techniques for dynamic vector compaction , 1995, Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

[8]  John A. Waicukauski,et al.  ATPG for ultra-large structured designs , 1990, Proceedings. International Test Conference 1990.

[9]  Elizabeth M. Rudnick,et al.  Sequential Circuit Test Generation in a Genetic Algorithm Framework , 1994, 31st Design Automation Conference.

[10]  Irith Pomeranz,et al.  On static compaction of test sequences for synchronous sequential circuits , 1996, DAC '96.

[11]  Alberto L. Sangiovanni-Vincentelli,et al.  Test generation for sequential circuits , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[12]  Michael H. Schulz,et al.  SOCRATES: a highly efficient automatic test pattern generation system , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[13]  Michael S. Hsiao,et al.  Automatic test generation using genetically-engineered distinguishing sequences , 1996, Proceedings of 14th VLSI Test Symposium.

[14]  Irith Pomeranz,et al.  Cost-Effective Generation of Minimal Test Sets for Stuck-at Faults in Combinational Logic Circuits , 1993, 30th ACM/IEEE Design Automation Conference.

[15]  Michael S. Hsiao,et al.  Fast algorithms for static compaction of sequential circuit test vectors , 1997, Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125).

[16]  Kewal K. Saluja,et al.  Methods for dynamic test vector compaction in sequential test generation , 1996, Proceedings of 9th International Conference on VLSI Design.

[17]  Ralph A. Marlett.  An Effective Test Generation System for Sequential Circuits , 1986, DAC 1986.

[18]  R Bevacqua,et al.  Implicit test sequences compaction for decreasing test application cost , 1996, Proceedings International Conference on Computer Design. VLSI in Computers and Processors.

[19]  Michael S. Hsiao,et al.  Sequential circuit test generation using dynamic state traversal , 1997, Proceedings European Design and Test Conference. ED & TC 97.

[20]  Janak H. Patel,et al.  Test compaction for sequential circuits , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[21]  Janak H. Patel,et al.  PROOFS: a fast, memory-efficient sequential circuit fault simulator , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[22]  Anand Raghunathan,et al.  Bottleneck removal algorithm for dynamic compaction and test cycles reduction , 1995, Proceedings of EURO-DAC. European Design Automation Conference.

[23]  Kewal K. Saluja,et al.  An Efficient Algorithm for Sequential Circuit Test Generation , 1993, IEEE Trans. Computers.

[24]  Michael H. Schulz,et al.  Advanced automatic test pattern generation and redundancy identification techniques , 1988, [1988] The Eighteenth International Symposium on Fault-Tolerant Computing. Digest of Papers.

[25]  Janak H. Patel,et al.  HITEC: a test generation package for sequential circuits , 1991, Proceedings of the European Conference on Design Automation..

[26]  Elizabeth M. Rudnick,et al.  Simulation-based techniques for dynamic test sequence compaction , 1996, ICCAD 1996.