A new static differential design style for hybrid SET–CMOS logic circuits

Single electron transistors (SETs) have ultra-small size, ultra-low power dissipation and unique Coulomb blockade oscillation characteristics which make them promising candidates for future technologies. However, SETs have extremely poor driving capabilities, low gain and background charges effect so that direct application to practical circuits is as yet almost impossible. A hybridization of existing CMOS technology with SETs is to overcome SET drawbacks and to investigate the robustness and fastness of the novel design in comparing with existing CMOS technology. The main objectives of this paper are to establish standard design styles for hybrid SET–CMOS logic circuits, and to propose a new static differential design style with superior performance at room temperature. This paper provides new SET–CMOS logic gates based on the differential design style, and also demonstrates the comparative performance study of full-adder circuits based on various SET–CMOS design styles. The comparison shows that the proposed differential logic circuit achieves a greater significance performance upon other SET–CMOS logic circuits. The final conclusion is made that the differential SET–CMOS style is more attractive design methodology for next generation VLSI/ULSI circuits.