A new flip-flop based on discrete-time parametric amplifier

Abstract This paper introduces a low power flip-flop based on the discrete-time parametric amplifier, with improved rise (fall) time, setup-time, hold-time, and area. Post-layout simulation result of the proposed flip-flop in a 180 nm CMOS technology with 3.33 GHz frequency illustrates about 21% of the power consumed by CML flip-flop and about 30% improvement in the clock-to-q delay. Also, the simulation shows improved rise (fall) time, lower data-to-q delay compared to dynamic CML and Footless flip-flop, lower area than Charge Steering flip-flops without the need for additional return-to-zero to non-return-to-zero conversion circuitry. When using this flip-flop as a slicer in a decision feedback equalizer (DFE) circuit of a serial link receiver of 1 m Nelco backplane channel, the post-layout simulation results show that the DFE circuit based on the parametric flip-flop has about 50% improvement of power consumption in comparison with the conventional CML DFE circuit in identical conditions.

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