KAHRISMA: A Novel Hypermorphic Reconfigurable-Instruction-Set Multi-grained-Array Architecture
暂无分享,去创建一个
Muhammad Shafique | Jörg Henkel | Lars Bauer | Jürgen Becker | Ralf König | Waheed Ahmed | Timo Stripf | J. Henkel | J. Becker | M. Shafique | Ralf König | Waheed Ahmed | L. Bauer | Timo Stripf
[1] Sharad Malik,et al. Architecture Description Languages for Retargetable Compilation , 2007, The Compiler Design Handbook, 2nd ed..
[2] Qiwei Zhang,et al. Implementing Non Power-of-Two FFTs on Coarse-Grain Reconfigurable Architectures , 2005, 2005 International Symposium on System-on-Chip.
[3] Rudy Lauwereins,et al. ADRES: An Architecture with Tightly Coupled VLIW Processor and Coarse-Grained Reconfigurable Matrix , 2003, FPL.
[4] Kingshuk Karuri,et al. Design Space Exploration of Partially Re-configurable Embedded Processors , 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.
[5] Muhammad Shafique,et al. A computation- and communication- infrastructure for modular special instructions in a dynamically reconfigurable processor , 2008, 2008 International Conference on Field Programmable Logic and Applications.
[6] Andreas Moshovos,et al. CHIMAERA: a high-performance architecture with a tightly-coupled reconfigurable functional unit , 2000, ISCA '00.
[7] Yurong Chen. Accelerating Video Feature Extractions in CBVIR on Multicore Systems , 2007 .
[8] R. Guerrieri,et al. XiSystem: a XiRisc-based SoC with reconfigurable IO module , 2005, IEEE Journal of Solid-State Circuits.
[9] Gerard J. M. Smit,et al. Overview of the 4S Project , 2005, 2005 International Symposium on System-on-Chip.
[10] Klaus D. Müller-Glaser,et al. MORPHEUS: Heterogeneous Reconfigurable Computing , 2007, 2007 International Conference on Field Programmable Logic and Applications.
[11] Itu-T and Iso Iec Jtc. Advanced video coding for generic audiovisual services , 2010 .
[12] Srivaths Ravi,et al. A Scalable Application-Specific Processor Synthesis Methodology , 2003, ICCAD 2003.
[13] Gerard J. M. Smit,et al. Lessons learned from designing the MONTIUM - a coarse-grained reconfigurable processing tile , 2004, 2004 International Symposium on System-on-Chip, 2004. Proceedings..
[14] Tulika Mitra,et al. An efficient framework for dynamic reconfiguration of instruction-set customization , 2007, CASES '07.
[15] Muhammad Shafique,et al. Run-time instruction set selection in a transmutable embedded processor , 2008, 2008 45th ACM/IEEE Design Automation Conference.
[16] Ben H. H. Juurlink,et al. Analyzing Scalability of Deblocking Filter of H.264 via TLP Exploitation in a New Many-Core Architecture , 2008, 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools.
[17] Heiko Schwarz,et al. Context-based adaptive binary arithmetic coding in the H.264/AVC video compression standard , 2003, IEEE Trans. Circuits Syst. Video Technol..
[18] Prabhat Mishra,et al. Architecture description languages for programmable embedded systems , 2005 .
[19] Frank Vahid,et al. Warp Processors , 2004, ACM Trans. Design Autom. Electr. Syst..
[20] Scott A. Mahlke,et al. An architecture framework for transparent instruction set customization in embedded processors , 2005, 32nd International Symposium on Computer Architecture (ISCA'05).
[21] Nikil D. Dutt,et al. Introduction of local memory elements in instruction set extensions , 2004, Proceedings. 41st Design Automation Conference, 2004..
[22] Paolo Bonzini,et al. Compiling custom instructions onto expression-grained reconfigurable architectures , 2008, CASES '08.
[23] Paul L. Master. Reconfigurable Hardware and Software Architectural Constructs for the Enablement of Resilient Computing Systems , 2006, IEEE 17th International Conference on Application-specific Systems, Architectures and Processors (ASAP'06).
[24] Joan Daemen,et al. AES Proposal : Rijndael , 1998 .
[25] Stamatis Vassiliadis,et al. Automatic selection of application-specific instruction-set extensions , 2006, Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '06).
[26] Muhammad Shafique,et al. Optimizing the H.264/AVC Video Encoder Application Structure for Reconfigurable and Application-Specific Platforms , 2010, J. Signal Process. Syst..
[27] Benjamin M. Brosgol. TCOLAda and the “Middle End” of the PQCC Ada compiler , 1980, SIGPLAN '80.
[28] Muhammad Shafique,et al. Run-time System for an Extensible Embedded Processor with Dynamic Instruction Set , 2008, 2008 Design, Automation and Test in Europe.