Low power-four quadrant CMOS analog multiplier for artificial neural networks

Artificial neural networks (ANN) consist of many neuron and synapse subcircuits which are massively parallel processing elements. The number of transistors and the power consumption of circuits with many synapses are important performance criteria in ANN applications. Analog multipliers have a great importance in analog signal processing. With their specifications of density, speed and low power consumption, they are used in the electronic realization of artificial neural networks. A low power (133 /spl mu/W), four quadrant analog multiplier with a low transistor count is proposed, particularly for artificial neural network applications. The circuit was designed using 1.5 /spl mu/m Tu/spl uml/bitak-Yital process parameters. The power supply of the circuit is /spl plusmn/5 V. The linear dynamic range of inputs is /spl plusmn/1 V.

[1]  Walid S. Saba,et al.  ANALYSIS AND DESIGN , 2000 .

[3]  Z. Wang,et al.  A CMOS four-quadrant analog multiplier with single-ended voltage output and improved temperature performance , 1991 .

[4]  J.N. Babanezhad,et al.  A 20-V four-quadrant CMOS analog multiplier , 1985, IEEE Journal of Solid-State Circuits.

[5]  James J. Clark,et al.  A four-quadrant CMOS analog multiplier for analog neural networks , 1994, IEEE J. Solid State Circuits.

[6]  Montree Siripruchyanun,et al.  A four-quadrant analog multiplier based on switched-capacitor and pulse-width amplitude modulation techniques , 2002, 9th International Conference on Electronics, Circuits and Systems.

[7]  H. F. Hamed,et al.  A new wideband BiCMOS four-quadrant analog multiplier , 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

[8]  E. Sanchez-Sinencio,et al.  A Resistorless Small Area, Low Power Cmos Four-quadrant Multiplier , 1996, 1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96.

[9]  Hussein Chible.  Analog circuit for synapse neural networks VLSI implementation , 2000, ICECS 2000. 7th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.00EX445).

[10]  F. Montecchi,et al.  Low voltage low power CMOS four-quadrant analog multiplier for neural network applications , 1996, 1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96.