High-performance sub-0.1-/spl mu/m CMOS with low-resistance T-shaped gates fabricated by selective CVD-W
暂无分享,去创建一个
This paper describes the high performance of sub-0.1-/spl mu/m T-shaped gate CMOS devices fabricated by using selective W growth. The W growth achieves low-resistance gates smaller than 0.1 /spl mu/m; counter doping achieves threshold voltage scaling, resulting in a ring-oscillator gate-delay time of 21 psec.
[1] J. Warnock,et al. A High Performance 0.25/spl mu/m CMOS , 1993, Symposium 1993 on VLSI Technology.