Customized simulated annealing based decision algorithms for combinatorial optimization in VLSI floorplanning problem

Modern very large scale integration technology is based on fixed-outline floorplan constraints, mostly with an objective of minimizing area and wirelength between the modules. The aim of this work is to minimize the unused area, that is, dead space in the floorplan, in addition to these objectives. In this work, a Simulated Annealing Algorithm (SAA) based heuristic, namely Simulated Spheroidizing Annealing Algorithm (SSAA) has been developed and improvements in the proposed heuristic algorithm is also suggested to improve its performance. Exploration capability of the proposed algorithm is due to the mechanism of reducing the uphill moves made during the initial stage of the algorithm, extended search at each temperature and the improved neighborhood search procedure. The proposed algorithm has been tested using two kinds of benchmarks: Microelectronics Center of North Carolina (MCNC) and Gigascale Systems Research Center (GSRC). The performance of the proposed algorithm is compared with that of other stochastic algorithms reported in the literature and is found to be efficient in producing floorplans with very minimal dead space. The proposed SSAA algorithm is also found more efficient for problems of larger sizes.

[1]  Wayne Wei-Ming Dai,et al.  General floorplanning with L-shaped, T-shaped and soft blocks based on bounded slicing grid structure , 1997, Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference.

[2]  Igor L. Markov,et al.  Fixed-outline floorplanning: enabling hierarchical design , 2003, IEEE Trans. Very Large Scale Integr. Syst..

[3]  Alberto Sangiovanni-Vincentelli,et al.  TimberWolf3.2: A New Standard Cell Placement and Global Routing Package , 1986, DAC 1986.

[4]  Chin-Chuan Han,et al.  A Parallel Simulated Annealing Approach for Floorplanning in VLSI , 2009, ICA3PP.

[5]  Chang-Tzu Lin,et al.  Robust fixed-outline floorplanning through evolutionary search , 2004, ASP-DAC.

[6]  A. Sangiovanni-Vincentelli,et al.  The TimberWolf placement and routing package , 1985, IEEE Journal of Solid-State Circuits.

[7]  Yao-Wen Chang,et al.  Corner sequence - a P-admissible floorplan representation with a worst case linear-time packing scheme , 2003, IEEE Trans. Very Large Scale Integr. Syst..

[8]  Ernest S. Kuh,et al.  Sequence-pair based placement method for hard/soft/pre-placed modules , 1998, ISPD '98.

[9]  Carl Sechen.  Chip-planning, placement, and global routing of macro/custom cell integrated circuits using simulated annealing , 1988, 25th ACM/IEEE, Design Automation Conference.Proceedings 1988..

[10]  Takeshi Yoshimura,et al.  An O-tree representation of non-slicing floorplan and its applications , 1999, DAC '99.

[11]  Yao-Wen Chang,et al.  TCG: a transitive closure graph-based representation for non-slicing floorplans , 2001, DAC '01.

[12]  Maolin Tang,et al.  A Genetic Algorithm for VLSI Floorplanning Using O-Tree Representation , 2005, EvoWorkshops.

[13]  C. L. Liu,et al.  A New Algorithm for Floorplan Design , 1986, DAC 1986.

[14]  D. F. Wong,et al.  Simulated Annealing for VLSI Design , 1988 .

[15]  H. Murata,et al.  Rectangle-packing-based module placement , 1995, ICCAD 1995.

[16]  Mineo Kaneko,et al.  VLSI/PCB placement with obstacles based on sequence-pair , 1997, ISPD '97.

[17]  Andrew B. Kahng,et al.  Classical floorplanning harmful? , 2000, ISPD '00.

[18]  Yao-Wen Chang,et al.  B*-Trees: a new representation for non-slicing floorplans , 2000, DAC.

[19]  Sachin S. Sapatnekar,et al.  Handbook of Algorithms for Physical Design Automation , 2008 .

[20]  Yoji Kajitani,et al.  Module placement on BSG-structure and IC layout applications , 1996, ICCAD 1996.

[21]  Yao-Wen Chang,et al.  Modern floorplanning based on B/sup */-tree and fast simulated annealing , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[22]  Martin D. F. Wong,et al.  FAST-SP: a fast algorithm for block placement based on sequence pair , 2001, ASP-DAC '01.

[23]  W. Dai,et al.  Arbitrary rectilinear block packing based on sequence pair , 1998, 1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287).

[24]  Takeshi Yoshimura,et al.  An enhanced perturbing algorithm for floorplan design using the O-tree representation , 2000, ISPD '00.

[25]  C. D. Gelatt,et al.  Optimization by Simulated Annealing , 1983, Science.

[26]  Yici Cai,et al.  Corner block list: an effective and efficient topological representation of non-slicing floorplan , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

[27]  Ting-Chi Wang,et al.  An optimal algorithm for floorplan area optimization , 1990, 27th ACM/IEEE Design Automation Conference.

[28]  Guolong Chen,et al.  A PSO-based intelligent decision algorithm for VLSI floorplanning , 2010, Soft Comput..

[29]  R. Otten.  Automatic Floorplan Design , 1982, DAC 1982.

[30]  Igor L. Markov,et al.  Fixed-outline floorplanning through better local search , 2001, Proceedings 2001 IEEE International Conference on Computer Design: VLSI in Computers and Processors. ICCD 2001.

[31]  Xin Yao,et al.  A Memetic Algorithm for VLSI Floorplanning , 2007, IEEE Transactions on Systems, Man, and Cybernetics, Part B (Cybernetics).