Exploiting Schedule Slacks for Rate-Optimal Power-Minimum Software Pipelining

Increasing power consumption in high performance processors and the proliferation of embedded systems demand new compiler techniques geared toward both high performance and low power. Software pipelining, an effective compiler optimization to exploit instruction level parallelism across loop iterations, has been studied extensively. However, previous software pipelining methods focus on performance only. This paper presents a software pipelining method that reduces power consumption while keeping performance optimality. This is accomplished as schedule slacks exist for non-critical instructions even in performance optimal schedules, and by exploiting the slack appropriately, it may be possible to reduce the number of functional units used in the schedule. This paper formulates the problem of minimizing power consumption in software pipelined loops as an integer linear programming (ILP) problem and experimented this approach in a re-engineered MIPSpro compiler. By executing the program generated by the re-engineered compiler on Wattch power simulator, we observe that our approach can reduce dynamic energy consumption of a set of kernels from SPEC benchmarks by up to 15.4% (8.5% on an average) in comparison with the existing scheduler of MIPSpro compiler, which strive only for high performance. The proposed approach is also helpful to reduce leakage power. With a leakage power reduction mechanism which applies power supply gating whenever possible, schedules generated by our approach consume up to 54.5% (or 31.8% on an average) less leakage power than that consumed by the MIPSpro compiler generated schedules. This work is supported in part by DARPA, contract number 1120-24596, SGI, Delaware Research Partnership(DRP) program, grant number 002672, and Intel Corp, grant number 2002-0814.