A Review of Super Junction LDMOS

Abstract Super Junction Lateral Double-diffused MOSFET (SJ-LDMOS) is one of the important attractive devices in high-voltage integrated circuit and power integrated circuit. However, the SJ-LDMOS is generally implemented on a low-resistance substrate, which always suffers from substrate-assisted depletion (SAD) effect, which thus degrades the performance of devices. A number of literatures have been published to solve the SAD effect and improve performance. This review summarizes the developments made in SJ-LDMOS based on bulk silicon, silicon on insulator, and silicon on sapphire in the last 10 years. Finally, the future work what researchers can do on the SJ-LDMOS also has been proposed.

[1]  데이비드 러셀 호아그,et al.  High Voltage Semiconductor Device , 2002 .

[2]  Bo Zhang,et al.  High voltage SOI SJ-LDMOS on composite substrate , 2009, 2009 International Conference on Communications, Circuits and Systems.

[3]  W. Marsden.  I and J , 2012 .

[4]  S.G. Nassif-Khalil,et al.  SJ/RESURF LDMOST , 2004, IEEE Transactions on Electron Devices.

[5]  Wanjun Chen,et al.  Novel SJ-LDMOS with partial N-buried layer for SPIC applications , 2006, 2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings.

[6]  Mi-Young Kim,et al.  Implementation of buffered Super-Junction LDMOS in a 0.18um BCD process , 2009, 2009 21st International Symposium on Power Semiconductor Devices & IC's.

[7]  J. Appels,et al.  High voltage thin layer devices (RESURF devices) , 1979, 1979 International Electron Devices Meeting.

[8]  Wenlian Wang.  SOI SJ-LDMOS with added fixed charges in buried oxide , 2010, 2010 International Conference on Microwave and Millimeter Wave Technology.

[9]  Lin Chen,et al.  SLOP-LDMOS - a novel super-junction concept LDMOS and its experimental demonstration , 2005, Proceedings. 2005 International Conference on Communications, Circuits and Systems, 2005..

[10]  Florin Udrea,et al.  A new class of lateral power devices for HVIC's based on the 3D RESURF concept , 1998, Proceedings of the 1998 Bipolar/BiCMOS Circuits and Technology Meeting (Cat. No.98CH36198).

[11]  K. Buddharaju,et al.  Superjunction Power LDMOS on Partial SOI Platform , 2007, Proceedings of the 19th International Symposium on Power Semiconductor Devices and IC's.

[12]  Bo Zhang,et al.  SJ-LDMOS with high breakdown voltage and ultra-low on-resistance , 2006 .

[13]  C.A.T. Salama,et al.  Super-junction LDMOST on a silicon-on-sapphire substrate , 2003 .

[14]  M. J. Kumar,et al.  Linearity and speed optimization in SOI LDMOS using gate engineering , 2009 .

[15]  C.A.T. Salama,et al.  CMOS compatible super junction LDMOST with N-buffer layer , 2005, Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005..

[16]  C.A.T. Salama,et al.  Super junction LDMOST in silicon-on-sapphire technology (SJ-LDMOST) , 2002, Proceedings of the 14th International Symposium on Power Semiconductor Devices and Ics.

[17]  J. Tihanyi,et al.  A new generation of high voltage MOSFETs breaks the limit line of silicon , 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

[18]  B. Zhang,et al.  A New Super Junction LDMOS with N+-Floating Layer , 2006, 2006 CES/IEEE 5th International Power Electronics and Motion Control Conference.

[19]  Markus Schmitt,et al.  A 600V 8.7Ohmmm 2 Lateral Superjunction Transistor , 2006, ISPSD 2006.

[20]  C.A.T. Salama,et al.  150-V class superjunction power LDMOS transistor switch on SOI , 2002, Proceedings of the 14th International Symposium on Power Semiconductor Devices and Ics.

[21]  Zhang Bo,et al.  New CMOS compatible super-junction LDMOST with n-type buried layer , 2007 .

[22]  Z. Li,et al.  High-Voltage SOI SJ-LDMOS With a Nondepletion Compensation Layer , 2009, IEEE Electron Device Letters.

[24]  Florin Udrea,et al.  3D RESURF double-gate MOSFET: a revolutionary power device concept , 1998 .

[25]  F. Udrea,et al.  Ultra-fast LIGBTs and superjunction devices in membrane technology , 2005, Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005..

[26]  Florin Udrea,et al.  An analytical model for the 3D-RESURF effect , 2000 .

[27]  Florin Udrea,et al.  Lateral unbalanced super junction (USJ)/3D-RESURF for high breakdown voltage on SOI , 2001, Proceedings of the 13th International Symposium on Power Semiconductor Devices & ICs. IPSD '01 (IEEE Cat. No.01CH37216).

[28]  Issa Batarseh,et al.  The Power MOSFET , 2011 .

[30]  Bo Zhang,et al.  Application of field plate in SLOP-LDMOS , 2010, 2010 International Conference on Communications, Circuits and Systems (ICCCAS).

[31]  T. Fujihira.  Theory of Semiconductor Superjunction Devices , 1997 .

[32]  C.A.T. Salama,et al.  Back-etched super-junction LDMOST on SOI , 2004, Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850).

[33]  Robert A. Scholtz,et al.  Performance Analysis of , 1998 .