A generic, configurable and efficient architecture for first and second generation discrete wavelet packet transform with ultra-high speed and low-cost FPGA implementation

This work is part of a broader project in the field of wireless sensor networks, in which the wavelet transform is at the core of the transmission functions. Our goal in this paper is to propose a new DWT architecture characterized by a high level of performance and a low cost design. This goal is achieved in particular thanks to the intelligent sharing of hardware resources between the different filters in the DWT algorithm. This paper presents the architectures developped for the first generation Discrete Wavelet Packet Transform (DWPT), based on the Mallat algorithm, and for the second generation DWPT, based on the lifting scheme. These archictures empower us to compute DWPT at high sampling rates (upto 750 Mega-samples per second) while requiring only limited hardware resources and no memory storage between or within the different depth stages of the DWPT / IDWPT (Inverse DWPT) transform.This work is part of a broader project in the field of wireless sensor networks, in which the wavelet transform is at the core of the transmission functions. Our goal in this paper is to propose a new DWT architecture characterized by a high level of performance and a low cost design. This goal is achieved in particular thanks to the intelligent sharing of hardware resources between the different filters in the DWT algorithm. This paper presents the architectures developped for the first generation Discrete Wavelet Packet Transform (DWPT), based on the Mallat algorithm, and for the second generation DWPT, based on the lifting scheme. These archictures empower us to compute DWPT at high sampling rates (upto 750 Mega-samples per second) while requiring only limited hardware resources and no memory storage between or within the different depth stages of the DWPT / IDWPT (Inverse DWPT) transform.

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