Bitstream Decompression for High Speed FPGA Configuration from Slow Memories

In this paper, we present hardware decompression accelerators for bridging the gap between high speed FPGA configuration interfaces and slow configuration memories. We discuss different compression algorithms suitable for a decompression on FPGAs as well as on CPLDs with respect to the achievable compression ratio, throughput, and hardware overhead. This leads to various decompressor implementations with one capable to decompress at high data rates of up to 400 megabytes per second while only requiring slightly more than a hundred look-up tables. Furthermore, we present a sophisticated configuration bitstream benchmark.

[1]  Viktor K. Prasanna,et al.  Configuration compression for FPGA-based embedded systems , 2005, IEEE Trans. Very Large Scale Integr. Syst..

[2]  Jürgen Teich,et al.  Real-Time Configuration Code Decompression for Dynamic FPGA Self-Reconfiguration , 2004, IEEE International Parallel and Distributed Processing Symposium.

[3]  I. Xilinx,et al.  Virtex-II Platform FPGA User Guide , 2002 .

[4]  Jürgen Teich,et al.  Platform-independent methodology for partial reconfiguration , 2004, CF '04.

[5]  Christian Haubelt,et al.  Modeling and Design of Fault-Tolerant and Self-Adaptive Reconfigurable Networked Embedded Systems , 2006, EURASIP J. Embed. Syst..

[6]  David Salomon,et al.  Data Compression: The Complete Reference , 2006 .

[7]  Tulika Mitra,et al.  Configuration bitstream compression for dynamically reconfigurable FPGAs , 2004, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..

[8]  James A. Storer,et al.  Data compression via textual substitution , 1982, JACM.

[9]  Zhiyuan Li,et al.  Don't Care discovery for FPGA configuration compression , 1999, FPGA '99.

[10]  Jürgen Teich,et al.  Searching RC5-Keys with Distributed Reconfigurable Computing , 2006, ERSA.

[11]  Steven D. Blostein,et al.  FPGA-Based Communications Receivers for Smart Antenna Array Embedded Systems , 2006, EURASIP J. Embed. Syst..

[12]  Zhiyuan Li,et al.  Configuration Compression for Virtex FPGAs , 2001, The 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'01).

[13]  David A. Huffman,et al.  A method for the construction of minimum-redundancy codes , 1952, Proceedings of the IRE.

[14]  J. Becker,et al.  Real-time configuration code decompression for dynamic FPGA self-reconfiguration , 2004, 18th International Parallel and Distributed Processing Symposium, 2004. Proceedings..

[15]  Abraham Lempel,et al.  A universal algorithm for sequential data compression , 1977, IEEE Trans. Inf. Theory.

[16]  Scott Hauck,et al.  Runlength compression techniques for FPGA configurations , 1999, Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines (Cat. No.PR00375).