Solving Sudoku in reconfigurable hardware

In this paper we explore the effectiveness of solution of computationally intensive problems in FPGA (Field-Programmable Gate Array) on an example of Sudoku game. Three different Sudoku solvers have been fully implemented and tested on a low-cost FPGA of Xilinx Spartan-3E family. The first solver is only able to deal with simple puzzles with reasoning, i.e. without search. The second solver applies breadth-first search algorithm and therefore has virtually no limitation on the type of puzzles which are solvable. We prove that despite the serial nature of implemented backtracking search algorithms, parallelism can be used efficiently. Thus, the suggested third solver explores the possibility of parallel processing of search tree branches and boosts the performance of the second solver. The trade-offs of the designed solvers are analyzed, the results are compared to software and to other known implementations, and conclusions are drawn on how to improve the suggested architectures.

[1]  Shing-Tai Pan,et al.  THE IMPLEMENTATION OF SPEECH RECOGNITION SYSTEMS ON FPGA-BASED EMBEDDED SYSTEMS WITH SOC ARCHITECTURE , 2011 .

[2]  T. Yato,et al.  Complexity and Completeness of Finding Another Solution and Its Application to Puzzles , 2003, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

[3]  Rainer G. Spallek,et al.  Solving Sudokus through an incidence matrix on an FPGA , 2010, 2010 International Conference on Field-Programmable Technology.

[4]  Iouliia Skliarova,et al.  A SAT solver using software and reconfigurable hardware , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

[5]  C. Gonzalez,et al.  An initial specific processor for Sudoku solving , 2009, 2009 International Conference on Field-Programmable Technology.

[6]  Kevin Skadron,et al.  Accelerating Compute-Intensive Applications with GPUs and FPGAs , 2008, 2008 Symposium on Application Specific Processors.

[7]  Wayne Luk,et al.  Performance Comparison of Graphics Processors to Reconfigurable Logic: A Case Study , 2010, IEEE Transactions on Computers.

[8]  Joël Ouaknine,et al.  Sudoku as a SAT Problem , 2006, ISAIM.

[9]  Jean-Paul Delahaye.  The science behind Sudoku. , 2006, Scientific American.

[10]  Ioannis Papaefstathiou,et al.  Architecture, Design, and Experimental Evaluation of a Lightfield Descriptor Depth Buffer Algorithm on Reconfigurable Logic and on a GPU , 2011, 2011 IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines.

[11]  Muhammad Mansoor Ahmed,et al.  FPGA-BASED HOUSEHOLDER IMPLEMENTATION FOR EFFICIENT EIGENVALUES CALCULATION , 2011 .

[12]  Valery Sklyarov,et al.  Implementation in FPGA of Address-Based Data Sorting , 2011, 2011 21st International Conference on Field Programmable Logic and Applications.

[13]  Pavlos Malakonakis,et al.  Exploitation of Parallel Search Space Evaluation with FPGAs in Combinatorial Problems: The Eternity II Case , 2011, 2011 21st International Conference on Field Programmable Logic and Applications.

[14]  Miltiadis Smerdis,et al.  An FPGA-based Sudoku Solver based on Simulated Annealing methods , 2009, 2009 International Conference on Field-Programmable Technology.

[15]  Ioannis Sourdis,et al.  The TU Delft sudoku solver on FPGA , 2009, 2009 International Conference on Field-Programmable Technology.