A Tri-level Current-Steering DAC Design with Improved Output-Impedance Related Dynamic Performance

This paper presents a design of a low-latency 12-bit linear tri-level current-steering digital-to-analogue-converter for use in continuous-time ADCs. The DAC design achieves 12-bit static linearity, while the combination of DAC slice impedance matching with a proposed compensation technique reduces output-impedance related distortion. The technique demonstrates ~10dB improvement in DAC dynamic performance at high frequencies over the Nyquist-band at 100MS/$s$. The DAC has been verified by simulation results in TSMC 1.2V 65nm CMOS technology.

[1]  Nan Sun,et al.  Dynamic Element Matching With Signal-Independent Element Transition Rates for Multibit $\Delta\Sigma$ Modulators , 2015, IEEE Transactions on Circuits and Systems I: Regular Papers.

[2]  Song Jia,et al.  Binary tree structure random Dynamic Element Matching technique in current-steering DACs , 2012, 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology.

[3]  Marcel J. M. Pelgrom,et al.  Matching properties of MOS transistors , 1989 .

[4]  Arthur H. M. van Roermund,et al.  Mismatch-based timing errors in current steering DACs , 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

[5]  Michiel Steyaert,et al.  A 10–Bit 1.6-GS/s 27-mW Current-Steering D/A Converter With 550-MHz 54-dB SFDR Bandwidth in 130-nm CMOS , 2010, IEEE Transactions on Circuits and Systems I: Regular Papers.

[6]  Michiel Steyaert,et al.  An Accurate Statistical Yield Model for CMOS Current-Steering D/A Converters , 2000, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353).

[7]  Bob Adams,et al.  A 108dB SNR 1.1mW Oversampling Audio DAC with a Three-Level DEM Technique , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[8]  K. Nguyen,et al.  A 108 dB SNR, 1.1 mW Oversampling Audio DAC With A Three-level DEM Technique , 2008, IEEE Journal of Solid-State Circuits.

[9]  Chung-Chih Hung,et al.  Glitch Energy Reduction and SFDR Enhancement Techniques for Low-Power Binary-Weighted Current-Steering DAC , 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[10]  Brendan Mullane,et al.  Bandwidth Enhancement to Continuous-Time Input Pipeline ADCs , 2018, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.