Codesign of a parallel architecture and an optimizing compiler backend: SIN rete processing as a case study

The move towards higher levels of abstraction in hardware design begins to blur the difference between hardware and software design. Nevertheless, the attractiveness of a software implementation is still defined by the much smaller abstraction gap between specification and implementation. Whereas, hardware design creates the possibility to exploit parallelism at a very fine level of granularity and thereby achieve tremendous performance gains with a moderate expenditure of hardware. This paper describes the joint design process leading to an ASIC chipset accelerating the execution of rulebased systems. The interaction between the algorithm used for software implementation and the parallel algorithm suited for hardware implementation is examined. An area efficient implementation of the programmable hardware was enabled by an application specific compiler backend. The heuristics applied by the optimising “code” generator are discussed quantitatively.

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