A software solution to estimate the SEU-induced soft error rate for systems implemented on SRAM-based FPGAs

SRAM-based FPGAs are very susceptible to radiation-induced Single-Event Upsets (SEUs) in space applications. The failure mechanism in FPGA's configuration memory differs from those in traditional memory device. As a result, there is a growing demand for methodologies which could quantitatively evaluate the impact of this effect. Fault injection appears to meet such requirement. In this paper, we propose a new methodology to analyze the soft errors in SRAM-based FPGAs. This method is based on in depth understanding of the device architecture and failure mechanisms induced by configuration upsets. The developed programs read in the placed and routed netlist, search for critical logic nodes and paths that may destroy the circuit topological structure, and then query a database storing the decoded relationship of the configurable resources and corresponding control bit to get the sensitive bits. Accelerator irradiation test and fault injection experiments were carried out to validate this approach.

[1]  Carl Carmichael.  Virtex FPGA series configuration and readback , 1999 .

[2]  Sergio D'Angelo,et al.  A tool for injecting SEU-like faults into the configuration control mechanism of Xilinx Virtex FPGAs , 2003, Proceedings 18th IEEE Symposium on Defect and Fault Tolerance in VLSI Systems.

[3]  M. Wirthlin,et al.  SEU-induced persistent error propagation in FPGAs , 2005, IEEE Transactions on Nuclear Science.

[4]  C.K. Filho,et al.  Improving Reliability of SRAM-Based FPGAs by Inserting Redundant Routing , 2005, 2005 8th European Conference on Radiation and Its Effects on Components and Systems.

[5]  P. Sundararajan,et al.  Consequences and Categories of SRAM FPGA Configuration SEUs , 2003 .

[6]  P. Graham,et al.  An Automated Approach to Estimating Hardness Assurance Issues in Triple-Modular Redundancy Circuits in Xilinx FPGAs , 2008, IEEE Transactions on Nuclear Science.

[7]  D. Bortolato,et al.  Errata to “Identification and Classification of Single-Event Upsets in the Configuration Memory of SRAM-Based FPGAs” , 2003 .

[8]  Glenn H. Chapman,et al.  Defect and Fault Tolerance in VLSI Systems , 2003 .

[9]  I. Xilinx.  Virtex series configuration architecture user guide , 2000 .

[10]  M. Alderighi,et al.  Soft Errors in SRAM-FPGAs: A Comparison of Two Complementary Approaches , 2008, IEEE Transactions on Nuclear Science.

[11]  M. Caffrey,et al.  Correcting single-event upsets through virtex partial configuration , 2000 .

[12]  L. Sterpone,et al.  A new analytical approach to estimate the effects of SEUs in TMR architectures implemented through SRAM-based FPGAs , 2005, IEEE Transactions on Nuclear Science.

[13]  Massimo Violante,et al.  Simulation-based analysis of SEU effects in SRAM-based FPGAs , 2004, IEEE Transactions on Nuclear Science.

[14]  Paul Graham,et al.  Accelerator validation of an FPGA SEU simulator , 2003 .

[15]  D. Bortolato,et al.  Simulation-based analysis of SEU effects in SRAM-based FPGAs , 2004 .

[16]  D. Merodio,et al.  Experimental Validation of a Tool for Predicting the Effects of Soft Errors in SRAM-Based FPGAs , 2007, IEEE Transactions on Nuclear Science.

[17]  Mehdi B. Tahoori,et al.  An Analytical Approach for Soft Error Rate Estimation of SRAM-Based FPGAs , 2004 .

[18]  D.L. McMurtrey,et al.  A Comparison of TMR With Alternative Fault-Tolerant Design Techniques for FPGAs , 2007, IEEE Transactions on Nuclear Science.

[19]  Sergio D'Angelo,et al.  Evaluation of Single Event Upset Mitigation Schemes for SRAM based FPGAs using the FLIPPER Fault Injection Platform , 2007, 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007).