Fast Bring-Up of an AI SoC through IEEE 1687 Integrating Embedded TAPs and IEEE 1500 Interfaces

Complex application specific SoC are being developed for hardware support artificial intelligence (AI) applications. Such a complex SoCs are integrating a large number of on-chip and off-chip memories, numerous cores and interfaces including in our case a hierarchy of embedded TAPs, as well as security measures and Design-For-Test (DFT) structures. In this case-study paper, we demonstrate using IEEE 1687-2014 (IJTAG) to integrate all these different components into a single, unifying methodology. From this, we derive the benefits of workflow efficiency and fast silicon bring-up. For example, we can report that silicon bring-up of the DFT of the entire SoC was completed in about 4 days, and other bring-up aspects of the Soc were also completed in very little time.

[1]  Wu Yang,et al.  A Case Study of Testing Strategy for AI SoC , 2019, 2019 IEEE International Test Conference in Asia (ITC-Asia).

[2]  Steven F. Oakland Position statement: TAPs all over my chips , 2002, Proceedings. International Test Conference.

[3]  Debashis Bhattacharya Hierarchical test access architecture for embedded cores in an integrated circuit , 1998, Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231).