Module placement with boundary constraints using O-tree representation

The O-tree representation needs linear computation effort to generate a corresponding layout, and exhibits a smaller upper bound of possible configurations. This paper addresses the problem of handling boundary constraints in the context of O-tree representation. This problem occurs when some modules need to be placed on the boundary of a chip so that they can be connected to the I/O pad. We derive several theoretical results and several polynomial methods to transform the O-tree into a feasible one and guarantee the following compaction not to destroy the feasibility. We also design a simulated annealing based algorithm to explore much more solution space. Experimental results on a benchmark are given.