On the optimization of ultra low power front-end interfaces for capacitive sensors

Abstract Traditionally, most of the sensor interfaces must be tailored towards a specific application. This design approach is inflexible and requires several iteration steps for new sensor applications. It usually results in high costs for low and medium quantity market products. On the other hand, generic interface design reduces the costs and may provide a handy solution for multisensor applications. This paper presents a new generic architecture for ultra low power (ULP) capacitive sensor systems. It consists of a sensor interface followed by a modulator. The sensor interface (capacitance to voltage converters and switched capacitor (SC) amplifier) works on a lower clock frequency, 8 kHz, than the modulator, 128 kHz, to achieve very low power consumption. A new capacitance to voltage converter with class AB and correlated double sampling (CDS) operation reduces the shunt conductance leakage. The system maintains a smart power management by adapting biasing currents, measurement time and duty cycle according to the needs of the application (parasitic element reduction, accuracy and speed). The proposed architecture provides an interface to a broad range of capacitive sensors. The simulations show that the readout circuitry consumes merely 29 μA in operational mode with a 3 V power supply.

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