论文信息 - Fine Time Resolution TDC Architectures -Integral and Delta-Sigma Types

Fine Time Resolution TDC Architectures -Integral and Delta-Sigma Types

This paper describes two time-to-digital converter (TDC) architectures for fine time resolution and good linearity: integral-type and delta-sigma TDC architectures. By investigating them, the similarity and difference between TDC and ADC architectures for fine resolution but slow measurement are clarified. Our integral-type TDC architectures are inspired by the integral-type ADC, and also the time-bases of the equivalent time sampling in the sampling oscilloscope: sequential sampling and random sampling. One TDC uses a sequential sampling time-base, and the other uses a random sampling time-base. Each of them consists of two trigger circuits, a sampling flip-flop, a binary counter and additional small logic circuit. Their circuit topologies, operation principles and simulation results as well as their comparison are presented. Also our delta-sigma TDC architecture is mentioned, and comparison between the integral and delta-sigma TDC architectures is discussed.

[1] Kazumi Hatayama,et al. Successive approximation time-to-digital converter with vernier-level resolution , 2016, 2016 IEEE 21st International Mixed-Signal Testing Workshop (IMSTW).

[2] Kensuke Kobayashi,et al. A New Coherent Sampling System with a Triggered Time Interpolation , 2001 .

[3] Michael Nelson. A New Technique for Low-Jitter Measurements Using Equivalent-Time Sampling Oscilloscopes , 2000, 56th ARFTG Conference Digest.

[4] Yujie Zhao,et al. Highly Efficient Waveform Acquisition Condition in Equivalent-Time Sampling System , 2018, 2018 IEEE 27th Asian Test Symposium (ATS).

[5] Kensuke Kobayashi,et al. A Quasi-Coherent Sampling Method for Wideband Data Acquisition , 2000, 56th ARFTG Conference Digest.

[6] Kosuke Machida,et al. Time-to-Digital Converter Architectures Using Two Oscillators with Different Frequencies , 2018, 2018 IEEE 27th Asian Test Symposium (ATS).