论文信息 - Study of electron and hole injection statistics of BE-SONOS NAND Flash

Study of electron and hole injection statistics of BE-SONOS NAND Flash

The electron and hole injection statistics of BE-SONOS NAND Flash is studied for the first time using a 75 nm charge-trapping NAND Flash test chip. By using the incremental step pulse programming (ISPP) method the impact of device variations are minimized and the electron number ( N ) fluctuation can be identified. We find that both electron and hole injection statistics well follow the Poisson statistics ( Sigma ∞ √N, where Sigma corresponds to the distribution width). However, due to the 3D fringing field effect the small transistors require more charge injection to obtain the same memory window, and this reduces the proportional factor of Sigma. We also found that the hole injection distribution is slightly broader than the electron injection, and can be explained by the lower charge centroid in nitride which leads to the larger proportional factor. Based on these results, we can also simulate the distribution for various technology nodes.

[1] Konstantin K. Likharev,et al. Layered tunnel barriers for nonvolatile memory devices , 1998 .

[2] Chih-Yuan Lu,et al. A Novel Gate-Sensing and Channel-Sensing Transient Analysis Method for Real-Time Monitoring of Charge Vertical Location in Sonos-Type Devices and its Applications in Reliability Studies , 2007, 2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual.

[3] Y. Shih,et al. BE-SONOS: A bandgap engineered SONOS with excellent performance and reliability , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

[4] M. Rosmeulen,et al. VARIOT: a novel multilayer tunnel barrier concept for low-voltage nonvolatile memory devices , 2003, IEEE Electron Device Letters.

[5] A. Visconti,et al. Ultimate Accuracy for the nand Flash Program Algorithm Due to the Electron Injection Statistics , 2008, IEEE Transactions on Electron Devices.

[6] Engineering the complete MANOS-type NVM stack for best in class retention performance , 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

[7] Tahone Yang,et al. Understanding STI edge fringing field effect on the scaling of charge-trapping (CT) NAND Flash and modeling of incremental step pulse programming (ISPP) , 2009, 2009 IEEE International Electron Devices Meeting (IEDM).