A WCDMA/WLAN digital polar transmitter with AM replica feedback linearization in 65nm CMOS

A 65nm CMOS digital polar transmitter for WCDMA and WLAN is presented, which consists of a 9bit digitally-controlled switch-capacitor polar modulator and a 6-bit power amplifier array with a proposed linearity-enhancement technique. Even without AM-AM pre-distortion, the transmitter system measures RMS-EVM of 2.83% and 4.07% for WCDMA and WLAN 54-Mb/s OFDM, respectively; while providing a peak output power of 20.4dBm with PAE 32.3%.

[1]  Xin He,et al.  A 45nm WCDMA transmitter using direct quadrature voltage modulator with high oversampling digital front-end , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

[2]  Jeffrey S. Walling,et al.  A Switched-Capacitor RF Power Amplifier , 2011, IEEE Journal of Solid-State Circuits.

[3]  Khurram Muhammad,et al.  A 24mm2 Quad-Band Single-Chip GSM Radio with Transmitter Calibration in 90nm Digital CMOS , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[4]  Ali M. Niknejad,et al.  An Efficient Mixed-Signal 2.4-GHz Polar Power Amplifier in 65-nm CMOS Technology , 2011, IEEE Journal of Solid-State Circuits.

[5]  A. Scuderi,et al.  A 25 dBm Digitally Modulated CMOS Power Amplifier for WCDMA/EDGE/OFDM With Adaptive Digital Predistortion and Efficient Power Control , 2009, IEEE Journal of Solid-State Circuits.

[6]  Meng-Chang Lee,et al.  All-digital PLL and GSM/EDGE transmitter in 90nm CMOS , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

[7]  Paul T. M. van Zeijl,et al.  A Digital Envelope Modulator for a WLAN OFDM Polar Transmitter in 90 nm CMOS , 2007, IEEE Journal of Solid-State Circuits.