SynAbs: model reduction tool for Verilog verification
暂无分享,去创建一个
Y. Mokhtari | S. Tahar | M. Zaki | S. Tahar | M. Zaki | Y. Mokhtari
[1] Mohamed Benmohamed,et al. Predicate Abstraction and Refinement for Model Checking VHDL State Machines , 2002, FMICS.
[2] Sofiène Tahar,et al. Syntax code analysis and generation for Verilog , 2003, CCECE 2003 - Canadian Conference on Electrical and Computer Engineering. Toward a Caring and Humane Technology (Cat. No.03CH37436).
[3] Kedar S. Namjoshi,et al. Syntactic Program Transformations for Automatic Abstraction , 2000, CAV.
[4] Thomas Kropf,et al. Introduction to Formal Hardware Verification , 1999, Springer Berlin Heidelberg.
[5] Edmund M. Clarke,et al. Counterexample-Guided Abstraction Refinement , 2000, CAV.
[6] Fausto Giunchiglia,et al. NUSMV: a new symbolic model checker , 2000, International Journal on Software Tools for Technology Transfer.
[7] Orna Grumberg,et al. Syntax-directed model checking of sequential programs , 2002, J. Log. Algebraic Methods Program..
[8] Edmund M. Clarke,et al. Model checking and abstraction , 1994, TOPL.
[9] Tiziano Villa,et al. VIS: A System for Verification and Synthesis , 1996, CAV.
[10] Dennis Dams,et al. Abstraction in Software Model Checking: Principles and Practice (Tutorial Overview and Bibliography) , 2002, SPIN.
[11] Hong Peng,et al. Model reduction based on value dependency , 2001, Proceedings 14th Annual IEEE International ASIC/SOC Conference (IEEE Cat. No.01TH8558).
[12] Constance L. Heitmeyer,et al. Model Checking Complete Requirements Specifications Using Abstraction , 2004, Automated Software Engineering.
[13] Patrick Cousot,et al. Abstract Interpretation Based Formal Methods and Future Challenges , 2001, Informatics.