A new membrane SOI power device

A new SOI high-voltage power device with a combination of Uniform and Variation in Lateral Doping profiles on Partial Membrane(UVLD PM SOI) is proposed. Its partial substrate under the drift region is etched to release the potential lines below the buried layer, combining uniform and variation in lateral doping profiles, resulting in an enhancement of breakdown voltage while achieving a low specific on-resistance. The simulation results indicate that breakdown voltage for UVLD PM SOI is twice as high as that of the conventional SOI with th a 3 mum thick buried oxide and 20 mum long drift region. In contrast to CamSem device, the maximal temperature decreases by 42 K and specific on-resistance greatly reduces for UVLD PM SOI with Lb=10 mum.

[1]  Baoxing Duan,et al.  New thin-film power MOSFETs with a buried oxide double step structure , 2006, IEEE Electron Device Letters.

[2]  F. Udrea,et al.  High voltage devices - a milestone concept in power ICs , 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

[3]  Bo Zhang,et al.  A Novel 700-V SOI LDMOS With Double-Sided Trench , 2007, IEEE Electron Device Letters.

[4]  S. Mukherjee,et al.  Realization of high breakdown voltage (>700 V) in thin SOI devices , 1991, [1991] Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs.

[5]  Akio Nakagawa,et al.  New 1200 V MOSFET structure on SOI with SIPOS shielding layer , 1998, Proceedings of the 10th International Symposium on Power Semiconductor Devices and ICs. ISPSD'98 (IEEE Cat. No.98CH36212).

[6]  Holger Kapels,et al.  Dielectric charge traps. A new structure element for power devices , 2000, 12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094).

[7]  Bo Zhang,et al.  New High-Voltage ( $>$ 1200 V) MOSFET With the Charge Trenches on Partial SOI , 2008, IEEE Transactions on Electron Devices.

[8]  Bo Zhang,et al.  A new structure and its analytical model for the electric field and breakdown voltage of SOI high voltage device with variable-k dielectric buried layer , 2007 .

[9]  Akio Nakagawa,et al.  Breakdown voltage enhancement for devices on thin silicon layer/silicon dioxide film , 1991 .