论文信息 - On the implementation of input-feedforward delta-sigma modulators

On the implementation of input-feedforward delta-sigma modulators

This brief addresses some practical issues on the implementation of the input-feedforward delta-sigma modulators. First, the timing constraint imposed by the input-feedforward path is identified and a possible method to relax the constraint is proposed. Second, the drawbacks of the analog adder needed before the quantizer are explained and a method to eliminate the adder is proposed

Ahmed Gharbiya | D. A. Johns

[1] Gabor C. Temes,et al. Understanding Delta-Sigma Data Converters , 2004 .

[2] G. Temes,et al. Wideband low-distortion delta-sigma ADC topology , 2001 .

[3] Kenneth W. Martin,et al. High-order multibit modulators and pseudo data-weighted-averaging in low-oversampling ΔΣ ADCs for broad-band applications , 2004, IEEE Trans. Circuits Syst. I Regul. Pap..

[4] C. S. Petrie,et al. A multibit sigma-delta ADC for multimode receivers , 2003, IEEE J. Solid State Circuits.

[5] S. Garverick,et al. A third-order multistage sigma-delta modulator with reduced sensitivity to nonidealities , 1991 .

[6] P. Hurst,et al. Double sampling in switched-capacitor delta-sigma A/D converters , 1990, IEEE International Symposium on Circuits and Systems.

[7] Pieter Rombouts,et al. An approach to tackle quantization noise folding in double-sampling ΣΔ modulation A/D converters , 2003, IEEE Trans. Circuits Syst. II Express Briefs.