Dual threshold delay model for nonlinear device characterization

We propose a dual threshold delay model for accurate timing definition for cell-based LSI designs by introducing dual threshold voltage definitions for each cell and by making cell delay and wire delay positive. Our model aims at high density and low power design of sub-half micron CMOS devices. Further more, this model solves negative delay problem in conventional delay definition at very slow slope and accurate delay handling becomes possible in logic simulation and logic synthesis.

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