A 9‐mW Continuous‐time Hybrid Active–Passive ΣΔ Modulator with 84‐dB Dynamic Range

A hybrid active-passive, continuous time (CT) sigma-delta (ΣΔ) modulator with a multibit quantizer is presented. The modulator is designed as a fifth-order, dual-loop architecture, allowing for a maximum quantizer delay of half a clock period. By removing the summing block before the quantizer as well as by introducing an active-passive hybrid loop filter, the design achieves high signal-to-noise ratio (SNR) comparable to a fourth-order active design while dissipating power equivalent to a third-order implementation. A data-weighted averaging (DWA) algorithm implemented with analog reference shuffling is utilized to suppress the mismatches in the current-steering digital-to-analog conversion (DAC) with no extra delay introduced between the quantizer and DAC. The chip, manufactured in a 1.8-V, 0.18-μm complementary metal oxide semiconductor (CMOS) process, experimentally achieves 79.5 dB peak SNR, 78 dB peak signal-to-noise-and-distortion ratio (SNDR), and 84-dB dynamic range over a 1-MHz signal bandwidth. The 0.43-mm 2 test chip consumes 9-mW of power when clocked at 128 MHz.

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