论文信息 - CACTI: an enhanced cache access and cycle time model

CACTI: an enhanced cache access and cycle time model

In a clock having a synchronous motor and a chime that is struck once evey half hour by a biased hammer assembly that is prevented from striking the chime except when a tab on the hammer falls into a notch on a wheel driven by the minute shaft, a chime shutoff is mounted on the back cover of the clock for movement between a chime "on" and a chime "off" position.

Norman P. Jouppi | Steven J. E. Wilton | N. Jouppi | S. Wilton

[1] Paul Penfield,et al. Signal Delay in RC Tree Networks , 1981, 18th Design Automation Conference.

[2] Rajiv V. Joshi,et al. A 2-ns cycle, 3.8-ns access 512-kb CMOS ECL SRAM with a fully pipelined architecture , 1991 .

[3] Mark Horowitz,et al. Timing Models for MOS Circuits , 1983 .

[4] Michael J. Flynn,et al. An area model for on-chip memories and its application , 1991 .

[5] T. Wada,et al. An analytical access time model for on-chip cache memories , 1992 .

[6] Norman P. Jouppi,et al. Tradeoffs in two-level on-chip caching , 1994, ISCA '94.