Field-programmable gate array testing method

The invention discloses a field-programmable gate array testing method and belongs to integrated circuit design in the field of microelectronics and the field of electronic design automation. The method includes generating a testing circuit file according to a field-programmable gate array chip structure; generating a testing circuit constraint file according to the field-programmable gate array chip structure; obtaining an integrated net list according to the testing circuit constraint file; obtaining a mapping circuit net list according to the testing circuit constraint file and the integrated net list; completing routing of the testing circuit file according to a post-layout circuit unit and the testing circuit constraint file; obtaining a code stream file; testing an FPGA chip according to the code stream file. According to the field-programmable gate array testing method, the testing circuit is subjected to integration, mapping, layout, routing and code stream generation under constraint of the circuit constraint file, and the code stream file required by verification and testing is generated. The field-programmable gate array testing method is capable of effectively achieving wafer testing after FPGA layout verification and tape-out.