This paper reports on the VLSI realization of a hierarchical MPEG-2 HDTV video decoder based on the Spatially Scalable Profile at High-1440 Level. The decoder is built at the Heinrich-Hertz-Institut within the ongoing joint R&D project `Hierarchical Digital TV Transmission' (HDTVT) and will be demonstrated during the international exhibition IFA 1995 in Berlin. One goal of the project is the demonstration of a compatible approach to HDTV with TV-HDCTV compatibility through spatial scalability. The decoder can be used within several scenarios among which are terrestrial broadcasting with graceful degradation and portable reception (through spatial and SNR scalability) besides the less demanding cable and satellite scenarios. Two chips are currently under development to achieve an integrated hardware solution for the hierarchical MPEG-2 video source decoder. These chips are presented and the overall system architecture chosen for the HDTVT decoder is explained. The design approach utilizes logic synthesis and an on board DSP based functional test is implemented to support the field trials. The paper shows that multi-chip HDTV decoders are feasible today. According to the technological progress being expected within the years to come, optimized single-chip decoders with less external memory can be realized until about 1998.