Verity - A formal verification program for custom CMOS circuits

In an effort to fully exploit CMOS performance, custom design techniques are used extensively in commercial microprocessor design. However, given the complexity of current generation processors and the necessity for manual designer intervention throughout the design process, proving design correctness is a major concern. In this paper we discuss Verity, a formal verification program for symbolically proving the equivalence between a high-level design specification and a MOS transistor-level implementation. Verity applies efficient logic comparison techniques which implicitly exercise the behavior for all possible input patterns. For a given register-transfer level (RTL) system model, which is commonly used in present-day methodologies, Verity validates the transistor implementation with respect to functional simulation and verification performed at the RTL level. ∗Copyright c ©1994 International Business Corporation This document has been published in the IBM Journal on Research and Development, January 1995.

[1]  Dennis W. Shaklee,et al.  Proceedings of the 25th ACM/IEEE Design Automation Conference , 1988, DAC 1988.

[2]  Edward H. Frank.  Switch-Level Simulation of VLSI Using a Special-Purpose Data-Driven Computer , 1985, DAC 1985.

[3]  Randal E. Bryant,et al.  Boolean Analysis of MOS Circuits , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[4]  Daniel Brand.  Verification of large synthesized designs , 1993, ICCAD.

[5]  Leendert M. Huisman,et al.  Simulating Pass Transistor Circuits Using Logic Simulation Machines , 1983, 20th Design Automation Conference Proceedings.

[6]  Srinivas Devadas,et al.  On The Verification of Sequential Machines at Differing Levels of Abstraction , 1987, 24th ACM/IEEE Design Automation Conference.

[7]  Keith Hanna,et al.  Specification and Verification using Higher-Order Logic , 1985 .

[8]  Lynn Conway,et al.  Introduction to VLSI systems , 1978 .

[9]  Edward H. Frank,et al.  Switch-Level Simulation of VLSI Using a Special-Purpose Data-Driven Computer , 1985, 22nd ACM/IEEE Design Automation Conference.

[10]  William H. Kautz,et al.  The Necessity of Closed Circuit Loops in Minimal Combinational Circuits , 1970, IEEE Transactions on Computers.

[11]  Wolfgang Kunz.  HANNIBAL: an efficient tool for logic verification based on recursive learning , 1993, ICCAD.

[12]  Sérgio Vale Aguiar Campos,et al.  Symbolic Model Checking , 1993, CAV.

[13]  Jacob A. Abraham,et al.  Probabilistic design verification , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[14]  David Blaauw,et al.  Functional abstraction of logic gates for switch-level simulation , 1991, Proceedings of the European Conference on Design Automation..

[15]  D. I. Cheng,et al.  Error Diagnosis for Transistor-Level Verification , 1994, 31st Design Automation Conference.

[16]  Randal E. Bryant,et al.  A Switch-Level Model and Simulator for MOS Digital Systems , 1984, IEEE Transactions on Computers.

[17]  Manuel Blum,et al.  Equivalence of Free Boolean Graphs can be Decided Probabilistically in Polynomial Time , 1980, Inf. Process. Lett..

[18]  Randal E. Bryant,et al.  Mapping switch-level simulation onto gate-level hardware accelerators , 1991, 28th ACM/IEEE Design Automation Conference.

[19]  Michael C. McFarland,et al.  Formal verification of sequential hardware: a tutorial , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[20]  Tom Melham,et al.  Hardware Verification using Higher−Order Logic , 1986 .

[21]  Aarti Gupta,et al.  Formal hardware verification methods: A survey , 1992, Formal Methods Syst. Des..

[22]  M.M. Denneau.  The Yorktown Simulation Engine , 1982, 19th Design Automation Conference.

[23]  Michael Monachino.  Design Verification System for Large-Scale LSI Designs , 1982, 19th Design Automation Conference.

[24]  Daniel K. Beece,et al.  The EVE companion simulator , 1990, Proceedings of the European Design Automation Conference, 1990., EDAC..

[25]  Masahiro Fujita,et al.  Variable ordering algorithms for ordered binary decision diagrams and their evaluation , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[26]  Sharad Malik.  Analysis of cyclic combinational circuits , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[27]  Richard Rudell.  Dynamic variable ordering for ordered binary decision diagrams , 1993, ICCAD.

[28]  William J. Dally,et al.  A Hardware Architecture for Switch-Level Simulation , 1985, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[29]  Carl Ebeling.  GeminiII: a second generation layout validation program , 1988, [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers.

[30]  Randal E. Bryant,et al.  Graph-Based Algorithms for Boolean Function Manipulation , 1986, IEEE Transactions on Computers.

[31]  Randal E. Bryant.  Extraction of gate level models from transistor circuits by four-valued symbolic analysis , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[32]  Gordon L. Smith,et al.  Boolean Comparison of Hardware and Flowcharts , 1982, IBM J. Res. Dev..

[33]  Randal E. Bryant,et al.  COSMOS: a compiled simulator for MOS circuits , 1987, DAC '87.

[34]  Jean Christophe Madre,et al.  Proving circuit correctness using formal comparison between expected and extracted behaviour , 1988, 25th ACM/IEEE, Design Automation Conference.Proceedings 1988..

[35]  Fumihiro Maruyama.  Hardware Verification , 1985, Computer.

[36]  Daniel G. Schweikert,et al.  Proceedings of the 29th ACM/IEEE Design Automation Conference , 1992, DAC 1992.

[37]  Srinivas Devadas,et al.  On the verification of sequential machines at differing levels of abstraction , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[38]  Edmund M. Clarke,et al.  Symbolic model checking for sequential circuit verification , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[39]  Timothy Kam,et al.  Comparing layouts with HDL models: a formal verification technique , 1992, Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors.

[40]  Srinivas Devadas,et al.  Probabilistic construction and manipulation of Free Boolean Diagrams , 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).