A rail‐to‐rail low‐power latch comparator with time domain bulk‐tuned offset cancellation for low‐voltage applications

[1]  Alessandro Trifiletti,et al.  CMOS Non-tailed differential pair , 2016, Int. J. Circuit Theory Appl..

[2]  Rasoul Dehghani,et al.  A process and temperature robust constant-gm input/output rail-to-rail op-amp , 2015, Microelectron. J..

[3]  Bo Liu,et al.  A high-temperature comparator with rail-to-rail input voltage range , 2013, 2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS).

[4]  Mohamad Sawan,et al.  Low power/low voltage high speed CMOS differential track and latch comparator with rail-to-rail input , 2000, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353).

[5]  Pamela Abshire,et al.  Floating gate comparator with automatic offset manipulation functionality , 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

[6]  Emmanuel M. Drakakis,et al.  An output code offset-free comparator for SAR ADCs based on non-linear preamplifier and CMOS inverters , 2013, Microelectron. J..

[7]  Fabian Khateb,et al.  0.3-V bulk-driven programmable gain amplifier in 0.18-µm CMOS , 2017, Int. J. Circuit Theory Appl..

[8]  Franco Maloberti,et al.  A 1 mV resolution 10 MS/s rail-to-rail comparator in 0.5 /spl mu/m low-voltage CMOS digital process , 1997, Proceedings of 1997 IEEE International Symposium on Circuits and Systems. Circuits and Systems in the Information Age ISCAS '97.

[9]  Pamela Abshire,et al.  A 1.2-GHz comparator with adaptable offset in 0.35-μm CMOS , 2008, IEEE Transactions on Circuits and Systems I: Regular Papers.

[10]  Chao Yuan,et al.  An ultra low-power rail-to-rail comparator for ADC designs , 2011, 2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS).

[11]  Akira Matsuzawa,et al.  A low-offset latched comparator using zero-static power dynamic offset cancellation technique , 2009, 2009 IEEE Asian Solid-State Circuits Conference.

[12]  Reza Lotfi,et al.  Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator , 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[13]  O. Shoaei,et al.  A 1-V MOSFET-only fully-differential dynamic comparator for use in low-voltage pipelined A/D converters , 2003, Signals, Circuits and Systems, 2003. SCS 2003. International Symposium on.

[14]  Tomasz Kulej,et al.  A 0.5 V bulk-driven voltage follower/DC level shifter and its application in class AB output stage , 2015, Int. J. Circuit Theory Appl..

[15]  Mehdi Habibi,et al.  Application of class D power amplifiers in low power potentiostat circuits , 2017, Int. J. Circuit Theory Appl..

[16]  Johan H. Huijsing,et al.  Low-voltage operational amplifier with rail-to-rail input and output ranges , 1989 .

[17]  Behzad Razavi,et al.  Design techniques for high-speed, high-resolution comparators , 1992 .

[18]  Guido Torelli,et al.  1-V Rail-to-Rail CMOS OpAmp With Improved Bulk-Driven Input Stage , 2007, IEEE Journal of Solid-State Circuits.

[19]  Chih-Cheng Hsieh,et al.  A new rail-to-rail comparator with adaptive power control for low power SAR ADCs in biomedical application , 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.

[20]  Horst Zimmermann,et al.  A 0.12μm CMOS Comparator Requiring 0.5V at 600MHz and 1.5V at 6GHz , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[21]  Mounir Boukadoum,et al.  Low-voltage, high-speed CMOS analog latched voltage comparator using the "flipped voltage follower" as input stage , 2011, Microelectron. J..

[22]  C. Svensson,et al.  A 10-bit 5-MS/s successive approximation ADC cell used in a 70-MS/s ADC array in 1.2-μm CMOS , 1994, IEEE J. Solid State Circuits.

[23]  K. Nagaraj.  Constant transconductance CMOS amplifier input stage with rail-to-rail input common mode voltage range , 1995 .

[24]  K. W. Current,et al.  A rail-to-rail input-range CMOS voltage comparator , 1997, Proceedings of 40th Midwest Symposium on Circuits and Systems. Dedicated to the Memory of Professor Mac Van Valkenburg.

[25]  Eisse Mensink,et al.  A Double-Tail Latch-Type Voltage Sense Amplifier with 18ps Setup+Hold Time , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[26]  Jeremy Holleman,et al.  A Low-Power High-Precision Comparator With Time-Domain Bulk-Tuned Offset Cancellation , 2013, IEEE Transactions on Circuits and Systems I: Regular Papers.

[27]  Marco Lanuzza,et al.  Gate-level body biasing for subthreshold logic circuits: analytical modeling and design guidelines , 2015, Int. J. Circuit Theory Appl..

[28]  Pamela Abshire,et al.  A floating-gate comparator with automatic offset adaptation for 10-bit data conversion , 2005, IEEE Transactions on Circuits and Systems I: Regular Papers.

[29]  Shouli Yan,et al.  A Robust Rail-to-Rail Input Stage with Constant-gm and Constant Slew Rate Using a Novel Level Shifter , 2007, 2007 IEEE International Symposium on Circuits and Systems.