论文信息 - A high-speed 50% power-saving half-swing clocking scheme for flip-flop with complementary gate and source drive

A high-speed 50% power-saving half-swing clocking scheme for flip-flop with complementary gate and source drive

A half-swing clocking scheme with a complementary gate and source drive was proposed for CMOS flip-flop to reduce the power consumption of the clock system by 43%, while keeping the flip-flop delay time to be the same as that of the conventional full-swing clocking scheme. The delay time of the preceding half stage of flip-flop using this scheme is less than half that using the previous half-swing clocking scheme.

Hong-June Park | Jin-Cheon Kim | Sanghoon Lee

[1] Satoshi Tanaka,et al. Half-Swing Clocking Scheme for 75% Power Saving in Clocking Circuitry , 1994, Proceedings of 1994 IEEE Symposium on VLSI Circuits.

[2] Hiroshi Kawaguchi,et al. A reduced clock-swing flip-flop (RCSFF) for 63% power reduction , 1998, IEEE J. Solid State Circuits.

[3] Lee-Sup Kim,et al. A 200 MHz 13 mm/sup 2/ 2-D DCT macrocell using sense-amplifying pipeline flip-flop scheme , 1994 .

[4] Dake Liu,et al. Power consumption estimation in CMOS VLSI chips , 1994, IEEE J. Solid State Circuits.