Analyzing internal-switching induced simultaneous switching noise

The internal-switching induced simultaneous switching noise (SSN) is studied in the paper. Unlike ground bounce caused by driving off-chip loading, both power-rail and ground-rail wire/pin impedances are important in evaluating internal SSN, and the double negative feedback mechanism should be accounted for. Based on the lumped-model analysis and taking into account the parasitic effects and velocity-saturation effect of MOS transistors, a novel analytical model is developed which includes both switching and non-switching gates. The proposed model is employed to analyze on-chip decoupling capacitance, wire/pin inductance effect and loading effect analytically. Good agreements with SPICE simulations are obtained for submicron technology.

[1]  Melvin A. Breuer,et al.  Test generation for ground bounce in internal logic circuitry , 1999, Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146).

[2]  R. Senthinathan,et al.  Negative feedback influence on simultaneous switching CMOS outputs , 1988, Proceedings of the IEEE 1988 Custom Integrated Circuits Conference.

[3]  J. Mayer.  Advanced packaging , 1986 .

[4]  Yungseon Eo,et al.  New simultaneous switching noise analysis and modeling for high-speed and high-density CMOS IC package design , 2000, ECTC 2000.

[5]  V.H. Champac,et al.  Switching noise due to internal gates: delay implications and modeling , 2000, Proceedings of the 2000 Third IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.00TH8474).

[6]  Ishiuchi,et al.  Alpha-Power Law MOSFET Model and its Applications to CMOS Inverter Delay and Other Formulas , 2004 .

[7]  H. B. Bakoglu,et al.  Circuits, interconnections, and packaging for VLSI , 1990 .

[8]  G. Carlson.  Signal and Linear System Analysis , 1992 .

[9]  Melvin A. Breuer,et al.  Analysis of ground bounce in deep sub-micron circuits , 1997, Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125).

[10]  S. R. Vemuru,et al.  Accurate simultaneous switching noise estimation including velocity-saturation effects , 1996 .

[11]  P. Larsson.  Power supply noise in future IC's: a crystal ball reading , 1999, Proceedings of the IEEE 1999 Custom Integrated Circuits Conference (Cat. No.99CH36327).

[12]  Christer Svensson,et al.  Noise in digital dynamic CMOS circuits , 1994 .

[13]  Patrik Larsson,et al.  di/dt Noise in CMOS Integrated Circuits , 1997 .