Implementation of pipelined multipliers on Xilinx FPGAs

In this paper we present an approach for handoptimized pipelined FPGA-multipliers, namely carry save array multipliers (CSM). By a detailed adaptation to the underlying architecture of XC4013E-3 FPGAs, we derive high throughput and compact implementation of FPGA-Multipliers. By means of a sophisticated pipelining scheme, clock frequencies of up to 96MHz are achievable for operand's wordthwidth of up to 10 bits.