Development of 2D Modeling Techniques for the Thermal Fatigue Analysis of Solder Joints of a Module Mounted in a 3D Cavity on a Printed Circuit Board

Unlike the common types of SMT packages such as BGA and QFP, the component under investigation is a module mounted in a cavity on a PCB with their lead- fingers hanged over the edges of the cavity. This PCB assembly has a 3D configuration in nature such that regular 2D modeling is not capable to solve the problem. However, it is impractical to perform a 3D thermal fatigue analysis for this structure due to the very limited time to market requirement in the industry. In order to solve this problem, a 2D finite element modeling methodology with the use of artificial elements (effective block) to supplement the necessary boundary conditions is proposed. The focus of this paper is put on the calculation of the material properties of the effective block, and also on the application of it to solve the current 3D thermal fatigue problem. The good matching between the 2D modeling results and those from experiments suggests that the proposed methodology is an effective one, in addition to its high efficiency inborn. As 3D modeling comprises larger complexity and requires much heavier computational effort, it is usual to perform 2D modeling before any 3D simulation work for preliminary results. Yet, the 3D condition can be largely degenerated when it comes down to the 2D level. The present study demonstrates that the use of effective blocks is a way of enhancing the applicability of 2D models for solving more complicated problems.

[1]  Jianmin Qu,et al.  Three-Dimensional Versus Two-Dimensional Finite Element Modeling of Flip-Chip Packages , 1999 .

[2]  F. Che,et al.  Lead free solder joint reliability characterization for PBGA, PQFP and TSSOP assemblies , 2005, Proceedings Electronic Components and Technology, 2005. ECTC '05..

[3]  John H. L. Pang,et al.  Flip chip on board solder joint reliability analysis using 2-D and 3-D FEA models , 2001 .

[4]  John H. L. Pang,et al.  Thermal cycling analysis of flip-chip solder joint reliability , 2001 .

[5]  S. Lee,et al.  Computational analyses on the effects of irregular conditions during accelerated thermal cycling tests on board level solder joint reliability , 2004, Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971).

[6]  D. Lau,et al.  Computational model validation with experimental data from temperature cycling tests of PBGA assemblies for the analysis of board level solder joint reliability , 2004, 5th International Conference on Thermal and Mechanical Simulation and Experiments in Microelectronics and Microsystems, 2004. EuroSimE 2004. Proceedings of the.

[7]  Xuejun Fan,et al.  Effect of finite element modeling techniques on solder joint fatigue life prediction of flip-chip BGA packages , 2006, 56th Electronic Components and Technology Conference 2006.

[8]  J. Lau,et al.  Solder Joint Reliability of BGA, CSP, Flip Chip, and Fine Pitch SMT Assemblies , 1996 .

[9]  Sidharth,et al.  Board level solder reliability vs. ramp rate & dwell time during temperature cycling , 2003, 2003 IEEE International Reliability Physics Symposium Proceedings, 2003. 41st Annual..