A spur-reduction technique in a fully integrated CMOS frequency synthesizer for 5-GHz WLAN SOC

A spur-reduction technique is presented to accomplish low reference spurs while maintaining fast settling time for a fully integrated 5-GHz frequency synthesizer. The proposed synthesizer architecture smoothly adapts the loop parameters according to different operating modes, so as to reduce the loop bandwidth in the locked state to further attenuate the reference spurs. In addition, a high-performance charge pump circuit is incorporated with the adaptive synthesizer to alleviate non-ideal effects that cause spurs. The synthesizer, operating with a supply voltage of 1.2 V in a 0.18-μm CMOS process, achieves a low reference spur level of −60 dBc and a fast settling time of 32 μs for a frequency jump of 220 MHz.

[1]  W. Rhee,et al.  Design of high-performance CMOS charge pumps in phase-locked loops , 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

[2]  横矢 智,et al.  The charge pump circuit of Pll , 1989 .

[3]  Shen-Iuan Liu,et al.  A spur-reduction technique for a 5-GHz frequency synthesizer , 2006, IEEE Transactions on Circuits and Systems I: Regular Papers.

[4]  H. Samavati,et al.  5-GHz CMOS wireless LANs , 2002 .

[5]  Shaojun Wu.  A low-noise fast-settling PLL frequency synthesizer for CDMA receivers , 2004, 2004 International Symposium on System-on-Chip, 2004. Proceedings..

[6]  Wang Ling Goh,et al.  Design and frequency/phase-noise analysis of a 10-GHz CMOS ring oscillator with coarse and fine frequency tuning , 2006 .

[7]  William J. Kaiser,et al.  A 900-MHz 2.5-mA CMOS frequency synthesizer with an automatic SC tuning loop , 2001 .

[8]  H. Gustat,et al.  An integrated CMOS RF synthesizer for 802.11a wireless LAN , 2003, IEEE J. Solid State Circuits.

[9]  C.S. Vaucher,et al.  An adaptive PLL tuning system architecture combining high spectral purity and fast settling time , 2000, IEEE Journal of Solid-State Circuits.