A 93 MHz, X86 microprocessor with on-chip L2 cache controller

This 3.5 M-transistor microprocessor uses a 0.5 /spl mu/m CMOS technology. The die is mounted on the package with a solder-bump technology. Using custom and routed blocks with 5-layer metal, a die size of 14.1/spl times/14.1 mm/sup 2/ is produced. At 4.0 V and 25/spl deg/C, the chip operates above 93 MHz. With a 1 MB cache of 12 ns SRAMs, performance is over 120 Winstones.