A NOVEL CIRCUIT REDUCTION TECHNIQUE TO DETERMINE THE RESPONSE OF THE ON-CHIP VLSI RC INTERCONNECT FOR RAMP INPUT EXCITATION

In present day sub-micron technology, reduction of circuit complexity of on-chip VLSI interconnects is an important issue for the analysis and verification of integrated circuits. In this paper, we present an exact method to compute the analytic time-domain response for a RC circuit including coupling capacitors for ramp input excitation. Accuracy and efficiency of the method is shown for various examples. In deep sub-micron VLSI technology, parasitic elements play an important role in the analysis of on-chip VLSI interconnects. These parasitic elements arise mainly due to the increased number of metal level, thinner metal width, increased wire height versus width ratio and smaller wire spacing. Interconnects are hereby modelled as RC circuit as shown in Figure 1.

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