Scalability of RF CMOS

The scalability of advanced CMOS processes for RF applications is presented from a circuit design and system integration perspective. The impact of transistor scaling and advanced interconnects on active device performance and passive component quality is examined. Key challenges pertaining to high-level integration are assessed, including reduced supply headroom and substrate noise coupling. Effective circuit techniques and technology options for overcoming some of these limitations are reviewed. In summary, while many key RF device parameters improve with CMOS scaling, the major setbacks of lower supply voltage and higher mask cost can only be justified for products integrating RF circuits with large baseband digital blocks.

[1]  S. Simon Wong,et al.  Analysis and optimization of accumulation-mode varactor for RF ICs , 1998, 1998 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.98CH36215).

[2]  B. Razavi,et al.  Stacked inductors and transformers in CMOS technology , 2001, IEEE J. Solid State Circuits.

[3]  B. Wooley,et al.  A CMOS RF power amplifier with parallel amplification for efficient power control , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

[4]  C. Patrick Yue,et al.  Design strategy of on-chip inductors for highly integrated RF systems , 1999, DAC '99.

[5]  C. H. Diaz,et al.  CMOS technology for MS/RF SoC , 2003 .

[6]  J. Sun,et al.  A 90 nm CMOS MS/RF based foundry SOC technology comprising superb 185 GHz f/sub T/ RFMOS and versatile, high-Q passive components for cost/performance optimization , 2003, IEEE International Electron Devices Meeting 2003.

[7]  John R. Long,et al.  Differentially driven symmetric microstrip inductors , 2002 .

[8]  Chih-Yuan Lee,et al.  An efficient noise isolation technique for SOC application , 2004, IEEE Transactions on Electron Devices.

[9]  M. Tsai,et al.  Device properties in 90 nm and beyond and implications on circuit design , 2003, IEEE International Electron Devices Meeting 2003.

[10]  P.W.H. de Vreede,et al.  RF-CMOS Performance Trends , 2000, 30th European Solid-State Device Research Conference.

[11]  S.S. Wong,et al.  A 0 dB-IL, 2140/spl plusmn/30 MHz bandpass filter utilizing Q-enhanced spiral inductors in standard CMOS , 2001, 2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185).

[12]  C. Yue,et al.  On-chip Spiral Inductors With Patterned Ground Shields For Si-based RF IC's , 1997, Symposium 1997 on VLSI Circuits.

[13]  S.S. Wong,et al.  Modeling and characterization of on-chip transformers , 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

[14]  L.F. Tiemeijer,et al.  Record Q spiral inductors in standard CMOS , 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

[15]  Ali Hajimiri,et al.  Fully integrated CMOS power amplifier design using the distributed active-transformer architecture , 2002, IEEE J. Solid State Circuits.

[16]  D.B.M. Klaassen,et al.  RF-distortion in deep-submicron CMOS technologies , 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).

[17]  Shen-Iuan Liu,et al.  Miniature 3-D inductors in standard CMOS process , 2002, IEEE J. Solid State Circuits.

[18]  S. Wong,et al.  A 0-dB IL 2140 + /-30 MHz Bandpass Filter Utilizing Q-enhanced Spiral Inductors in Standard CMOS , 2001 .

[19]  S.S. Wong,et al.  Integrated CMOS transmit-receive switch using LC-tuned substrate bias for 2.4-GHz and 5.2-GHz applications , 2004, IEEE Journal of Solid-State Circuits.

[20]  R. Havens,et al.  Noise modeling for RF CMOS circuit simulation , 2003 .